1. Field of the Invention
This invention relates to semiconductor elements and wafer level chip size packages (WLCSP) therefor.
This application claims priority on Japanese Patent Applications Nos. 2004-158984, 2004-72375, 2004-80837, 2004-175262, 2004-173986, and 2004-351806, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In semiconductor devices such as LSI devices, integrated circuits such as transistors and various electronic components are formed on surfaces of semiconductor chips, which thus generate heat when operated. In order to avoid error and malfunction due to excessive heat generated in semiconductor chips, various heatsink structures and heat dissipation structures for effectively dissipating heat from semiconductor devices have been developed. For example, Japanese Patent Application Publication No. 2002-158310 teaches a semiconductor device equipped with a heat dissipation structure in which heat dissipation electrodes, which are connected with a board, dissipate heat generated by the surface of a semiconductor chip towards the board via an insulating resin (or an insulating layer). In this semiconductor device, the surface areas and side areas of the semiconductor chip are covered with the insulating resin (or insulating layer).
In addition, Japanese Patent Application Publication No. 2001-77236 teaches a semiconductor device equipped with a heat dissipation structure in which a relatively large amount of heat generated by a pad serving as a power source is dissipated via under-fill materials formed on the surface of a semiconductor element by means of heat dissipation patterns (corresponding to wiring portions) of a film substrate, which is arranged in the peripheral portion of the surface of the semiconductor element. In this semiconductor device, wiring portions are formed beside the surface of the semiconductor chip in which integrated circuits are formed.
Wafer level chip size packages (WLCSP) are manufactured such that before a wafer is cut into numerous individual semiconductor chips, wiring portions and electrode portions for establishing electric connections between semiconductor chips and boards are formed on surfaces of semiconductor chips and are enclosed in resins. In WLCSP, wiring portions, electrode portions, and insulating portions are formed at desired positions so that they do not project beyond side areas of a semiconductor chip. This realizes downsizing of a semiconductor device.
Both of the semiconductor device disclosed in Japanese Patent Application Publication No. 2002-158310, in which side areas of a semiconductor chip are enclosed in an insulating layer, and semiconductor device disclosed in Japanese Patent Application Publication No. 2001-77236 are not suited to WLCSP.
Conventionally, WLCSP is not equipped with a heat dissipation structure allowing efficient dissipation of heat generated by a semiconductor chip. Hence, it is strongly demanded that WLCSP be equipped with an effective heat dissipation structure in order to improve the reliability of semiconductor devices.
Due to recent developments regarding IC devices and LSI devices, which are highly advanced to realize high-speed processing and high integration of circuit elements, various types of structures regarding chips and packages realizing efficient heat dissipation from semiconductor devices have been developed and put into practical uses.
Great advances have been achieved in reducing sizes, thicknesses, and weights of electronic devices such as notebook computers and cellular phones equipped with digital cameras. As for chip housings for semiconductor elements, chip size packages (CSP) are recently substituted for conventional dual in-line packages (DIP).
For example, chip size packages (CSP) are designed such that semiconductor elements are connected to carrier substrates via metal bumps, and metal bumps used for attaching semiconductor elements onto printed-circuit boards are formed on the lower surfaces of the carrier substrates. Recent developments bring wafer level chip size packages (WLCSP) to have metal pads, allowing connections with external devices, which are formed on prescribed surfaces (or electronic-circuit fabricated surfaces) of semiconductor substrates on which electronic circuits are formed.
In addition, various structures have been developed to increase heat dissipation abilities for semiconductor elements in conventional chip size packages. For example, Japanese Patent Application Publication No. H10-321775 teaches a heatsink structure in which a thermal conduction sheet attached to a planar surface opposite to a prescribed surface of a CPS is brought into contact with a metal heatsink having a plurality of channels, which engage with metal heatsink plates to dissipate heat generated by a semiconductor element. Japanese Patent Application Publication No. H11-67998 teaches a heatsink structure in which an irregularities film having irregularities realizing height differences is formed on a planar surface opposite to a prescribed surface of a CSP so as to dissipate heat generated by a semiconductor element.
In the heatsink structure disclosed in Japanese Patent Application Publication No. H10-321775 in which metal heatsink plates are attached to the planar surface opposite to the prescribed surface of the CSP, heat dissipation effects must be limited due to the limited area of the planar surface.
In the heatsink structure disclosed in Japanese Patent Application Publication No. H11-67998, heat dissipation effects can be increased because the overall area is increased due to irregularities formed on the planar surface; however, there still remains a problem due to the limited heat dissipation effects thereof.
The conventional WLCSP has a very narrow surface area, which does not provide space for arranging a marking space thereon. This causes difficulty for the human operator to discriminate the direction of the semiconductor element.
Conventionally, semiconductor chips are mounted on boards in two steps, that is, a first step for realizing temporary bonding using the adhesive and a second step for realizing fixed bonding using the solder. This makes it very difficult for the manufacturer to reduce the production cycle in manufacturing of semiconductor chips and to reduce the manufacturing cost therefor. In addition, it is very difficult to downsize manufacturing machines, which causes bottlenecks in reducing the manufacturing cost. For this reason, various methods have been developed to efficiently mount semiconductor chips onto boards by use of magnetic materials and are put into practical uses, which are disclosed in the following documents, for example.                Japanese Patent Application Publication No. 2002-57433;        Japanese Patent No. 2,699,938;        Japanese Patent Application Publication No. H04-113690; and        Japanese Patent Application Publication No. H02-134894.        
Conventional methods for mounting semiconductor chips onto boards by using magnetic materials will be described with reference to FIGS. 20 and 21.
FIG. 35 is a cross sectional view showing a first example of the mounting method, wherein reference numeral 201 designates a chip module, and reference numeral 202 designates a wiring board on which the chip member 201 is mounted. The chip module 201 is designed such that a pair of electrode terminals 204 are attached to both sides of a chip substrate 203 on which an electronic circuit is formed; a permanent magnet 205 is adhered to the bottom of the chip substrate 203; and a sealing member 206 is formed on the upper surface of the chip substrate 203. The wiring board 202 is designed such that electrode patterns 208 are formed at prescribed positions on a substrate 207 on which wiring patterns (not shown) are formed; and a magnetic material 209 is arranged between the electrode patterns 208.
In procedures for mounting the chip module 201 onto the wiring board 202, the chip module 201 is arranged above the wiring board 202 so as to establish positioning between the electrode terminals 204 and the electrode patterns 208; then, the chip module 201 is moved downward so that the electrode terminals 204 are brought into contact with the electrode patterns 208, whereby it is possible to complete mounting procedures. Herein, the permanent magnet 205 of the chip module 201 attracts the magnetic material 209 of the wiring board 202, whereby it is possible to securely fix the chip module 201 to the wiring board 202 with prescribed positioning therebetween.
FIG. 36 is a cross sectional view showing a second example of the mounting method, wherein reference numeral 211 designates an IC chip, and reference numeral 212 designates a printed-circuit board. Herein, a plurality of electrode pads 213 are formed on a prescribed surface 211a of the IC chip 211, and magnetic materials 214 are embedded in the prescribed surface 211a of the IC chip 211. Wiring patterns 215 are formed on the printed-circuit board 212, and magnetic materials 216 are embedded in the printed-circuit board 212. In addition, solder balls 217 for establishing electric connections with the wiring patterns 215 are affixed onto the electrode pads 213.
In procedures for mounting the IC chip 211 onto the printed-circuit board 212, the solder balls 217 are affixed onto the electrode pads 213 of the IC chip 211; then, the IC chip 211 is positioned above the printed-circuit board 212 so as to establish positioning between the solder balls 217 and the wiring patterns 215; thereafter, the solder balls 217 are melted so that the IC chip 211 is securely mounted on the printed-circuit board 212. Herein, the magnetic materials 214 and 216 are both magnetized, so that the IC chip 211 is fixed to the printed-circuit board 212 with prescribed positioning therebetween.
The aforementioned methods require processes for positioning the permanent magnet 205 and the magnetic materials 209, 214, and 216 as well as processes for magnetizing the magnetic materials 209, 214, and 216. This increases the number of parts and the number of manufacturing processes, which in turn increase the manufacturing cost. When the permanent magnet 205 and the magnetic materials 209, 214, and 216 are changed in positioning, it is necessary to re-design products, which causes excessive cost in designing.
Before the chip module 201 is mounted on the wiring board 202 as shown in FIG. 35, it is necessary to attach the permanent magnet 205 to the chip module 201 and to correspondingly attach the magnetic material 209 to the wiring board 202, wherein due to the provision of the permanent magnet 205 and the magnetic material 209, the product should be increased in the overall height and volume, which causes unwanted limitations against the downsizing and thickness reduction of the product.
In order to mount the IC chip 211 incorporating the magnetic materials 214 onto the printed-circuit board 212 incorporating the magnetic materials 216, the thickness of the IC chip 211 must be increased to be greater than the thickness of the magnetic materials 214, and the thickness of the printed-circuit board 212 must be increased to be greater than the thickness of the magnetic materials 216. This causes unwanted limitations against the downsizing and thickness reduction of the product.
In WLCSP, integrated circuits are formed in a matrix form on the surface of a silicon wafer (or a semiconductor wafer), which is subjected to mirror surface processing, in accordance with thin-film formation techniques, lithography techniques, and etching techniques, wherein bumps and protective insulating films are formed on integrated circuits; thereafter, the semiconductor wafer is cut into individual pieces along scribing lines by use of a dicing saw and the like.
In the aforementioned manufacturing process, it is necessary to identify semiconductor wafers in order to manage WLCSP products in units of lots. Japanese Patent Application Publication No. H02-125412 teaches a semiconductor wafer having a bar code, which is put into practical use.
FIG. 41 is a perspective view showing an example of a semiconductor wafer having bar codes, wherein a dicer blade 302 is used to perform cutting on prescribed areas in proximity to an orientation flat 301a of a semiconductor wafer 301 or on peripheral areas of the semiconductor wafer 301, thus forming bar-like hollows 303a, 303b, . . . , all of which collectively server as a bar code 303.
In order to manage individual WLCSP products, identification codes for product management are formed on surfaces opposite to prescribed surfaces of packages in which electronic circuits are formed.
FIG. 42 is a perspective view showing an example of a package (i.e., a WLCSP 304) having identification codes, wherein an ink dot laser printer is used to print identification codes 306 representing a production code and characteristics on a backside surface 304a opposite to a prescribed surface of the WLCSP 4 on which bumps 305 are formed.
FIG. 43 is a perspective view showing another example of a package (i.e., a WLCSP 307) having identification codes, wherein a laser processing machine is used to form irregularities (i.e., identification codes 308) representing a product code and characteristics on a backside surface 307a opposite to a prescribed surface of the WLCSP 307 on which bumps 305 are formed.
The WLCSP 304 in which the identification codes 306 are printed using ink may suffer from various problems in which due to various factors such as dispersions of printing of ink, degrading of ink, and power fluctuations of the ink dot laser printer, the identification codes 306 are deviated in concentration and become unclear in reading. This causes error, malfunction, and difficulty in reading with regard to the identification codes 306. In addition, the WLCSP 304 requires a specially designed machine, i.e., an ink dot laser printer, in order to print the identification codes 306, which is troublesome.
The WLCSP 307 in which a laser processing machine is used to form the identification codes 308 may suffer from various problems in which due to various factors such as dispersions of irregularities and power fluctuations of the laser processing machine, the identification codes 308 are deviated in concentration and become unclear in reading. This causes error, malfunction, and difficulty in reading with regard to the identification codes 308. In addition, the WLCSP 307 requires a specially designed machine, i.e., a laser processing machine, in order to form the identification codes 308 realized by irregularities.
Due to technological advances of cellular phones and information terminals, which are reduced in sizes and weights and are highly advanced in performance, it is demanded that LSI devices and semiconductor devices be packaged with high integration and density of circuits and components. Wafer level chip size packages (WLCSP) are designed to realize highly integrated semiconductor devices, wherein wafer treatment and packaging are integrated in manufacturing.
FIG. 50 is a cross sectional view showing a semiconductor device encapsulated in a WLCSP, wherein re-wiring layers 477 are connected with pad electrodes (not shown) formed on a semiconductor chip 453; metal posts 480 enclosed in an enclosed resin 473 are formed on the re-wiring layers 477; and external terminals 481 such as solder balls are attached to the surfaces of the metal posts 480. This is disclosed in a magazine entitled “Nikkei Micro Device”, p.p. 44-71, 1998 August issue published in Japan. Japanese Patent Application Publication No. 2000-216184 teaches a first modification adapted to the semiconductor device in which metal posts are embedded in shield layers formed inside of openings of resins. Japanese Patent Application Publication No. 2001-244372 teaches a second modification adapted to the semiconductor device in which metal posts have spherical shapes.
However, the aforementioned semiconductor device and its first modification teach that external terminals whose diameters are greater than those of metal posts are attached onto the ‘columnar’ metal posts, wherein diameters of post bases (see 477b) for re-wiring layers are substantially identical to those of metal posts. This indicates a relatively great ratio of the area that the post bases occupy the re-wring layers, so that the re-wiring layers are limited in areas used for re-drawing of wires. Due to such a relatively small degree of freedom regarding re-wiring (or re-drawing of wires), the aforementioned structure have difficulty in coping with complicated arrangement of external terminals in LSI devices. In addition, this limits the total density of external terminals (i.e., the number of external terminals per unit area).
The freedom of degree regarding re-wiring may be improved by adopting multi-layered structures to re-wiring layers. However, this may greatly push up the manufacturing cost, which is inconvenient for manufacturers.
The second modification may be advantageous in that by forming metal posts in spherical shapes, metal posts serving as terminal bases are reduced in areas of surfaces lying close to external terminals. However, the reduction of the terminal base causes a reduction of the joining strength of the external terminal, whereby the semiconductor device should be degraded in reliability. In addition, ‘spherical’ metal posts may be easily destructed or easily separated off from the semiconductor chip.
Japanese Patent Application Publication No. 2001-94000 teaches an example of a semiconductor device enclosed in a chip size package (CPS) in which a semiconductor chip is connected with a base substrate via external terminals for establishing electric connection with a printed-circuit board.
Japanese Patent Application Publication No. 2003-124389 teaches an example of a wafer level chip size package (WLCSP) realizing further downsizing of a semiconductor device including a semiconductor substrate in which external terminals are formed on a prescribed surface for fabricating electronic circuits.
FIG. 61 is a perspective view showing a chip size package (CSP) 501; and FIG. 62 is a cross sectional view of the CSP 501, wherein a semiconductor chip 503 is electrically connected with circuits and wires formed on the surface of a base substrate 502; an insulating resin tape 504 is adhered to the backside of the base substrate 502; metal bumps 505 for establishing electric connections with the semiconductor chip 503 are exposed on the resin tape 504; and V-shaped channel portions 506 are formed and elongated two-dimensionally on the surface and backside of the base substrate 502.
Due to the formation of the V-shaped channel portions 506 on the surface and backside of the base substrate 502, the CSP 501 is disadvantageous in that the base substrate 502 is slightly reduced in rigidity and the end portions thereof may be easily deformed. When the CSP 501 is mounted on a printed-circuit board by heating reflow, end portions of the base substrate 502 are easily deformed in response to the bending of the printed-circuit board, whereby the metal bumps 505 may not be destroyed and are not likely to be badly deformed towards adjacent lands on the printed-circuit board.
FIG. 63 is a cross sectional view showing a conventionally known example of a WLCSP 511, wherein an integrated circuit 513 is formed on a surface 512a of a silicon substrate 512; a resin enclosing layer 514 composed of an insulating resin is formed to entirely cover the surface 512a including the integrated circuit 513; and solder bumps (or electrodes) 515 for establishing electric connections with the integrated circuit 513 are partially exposed on the surface 514a of the resin enclosed layer 514.
The area occupied by the WLCSP 511 is substantially identical to the overall surface area of the silicon substrate 512. Compared with the CSP 501, the WLCSP 511 is reduced in the area for fabricating electronic circuits and is reduced in size.
The aforementioned CSP 501 in which the V-shaped channel portions 506 are formed on the surface and backside of the base substrate 502 can reliably prevent solder bridges and lines from being destroyed and broken due to the curvature of the printed-circuit board. However, it is very difficult to avoid the occurrence of the entire curvature of the CSP 501 including the semiconductor chip 503.
That is, the formation of the V-shaped channel portions 506 on the surface and backside of the base substrate 502 may not adequately avoid the entire curvature of the CSP 501 including the semiconductor chip 503.
Similar to the CSP 501, it is very difficult to avoid the occurrence of the entire curvature of the WLCSP 511 including the silicon substrate 512.